Conventionally, a semiconductor integrated circuit device provided with a power transistor (a so-called power IC) sometimes needs to pass a relatively high current through the power transistor depending on its specifications. Thus, as shown in FIG. 5, a conventional semiconductor integrated circuit device adopts a configuration in which one end of the power transistor is connected in parallel to a plurality of pads and these pads are connected to a common frame (an external terminal) by wire bonding, in other words, a configuration in which a current is divided among a plurality of bonding wires.
As a conventional technology related to what has been described thus far, a semiconductor device for high current in which a large number of unit cells are arranged in parallel is disclosed and proposed (see, for example, Patent Publication 1). The semiconductor device disclosed therein has a chip configuration in which at least one of main electrode regions of this semiconductor device is divided into at least two and more independent bonding pad regions, and mutually independent bonding wires are connected individually to the bonding pads at one end thereof and connected to a common external terminal at the other end thereof.
Patent Publication 1 JP-A-H9-266226